1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device, and more specifically, concerns a semiconductor integrated circuit that is provided with a testing circuit for carrying out a test on a semiconductor memory device.
2. Description of the Background Art
Most of semiconductor devices have a redundant memory cell, and when there is a defective memory cell in one portion of the memory cell, it replaces the defective portion with the redundant memory cell so as to repair the defective chip.
FIG. 28 is a schematic block diagram that shows the structure of a redundant circuit that is installed with respect to a memory array section 8010 of such a semiconductor memory device.
One memory cell in memory array 8010 is selected by a row address signal RA0-13 and a column address signal CA0-8 that are externally inputted. In this one memory cell thus selected, during a writing operation, data supplied to a data input/output terminal DQ (not shown) is written. Moreover, during a reading operation, read data is outputted from memory array 8010 to this data input/output terminal DQ.
A row decoder 8020 selects a memory cell corresponding to one row to be read or written in accordance with the inputted row address. Moreover, a column decoder 8030 carries out a selection of one column based upon a column address inputted so that, among memory cells corresponding to one row selected by the row address, one memory cell is further selected.
The above-mentioned detection of a defective memory cell and an analysis for replacing the defective memory cell with a redundant memory cell array are generally carried out by a memory tester that is placed outside of the semiconductor memory device.
In recent years, however, a semiconductor memory device or a semiconductor device having a semiconductor memory device, which is provided with a so-called built-in type testing device that has a build-in signal generator within a semiconductor memory device to be tested or within a semiconductor device on which a semiconductor memory device is installed so that the testing process is carried out without using the memory tester, has been manufactured.
However, in such a semiconductor memory device or a semiconductor device provided with such a build-in testing device, although it is possible to carry out the test for determining as to whether or not any detective memory exists, it is difficult to carry out a test for achieving a redundant analysis on the device itself. This is because, as described earlier, a fail memory for storing the addresses of defective memory cells requires a memory of which capacity is as large as the semiconductor memory device or the built-in the semiconductor memory device in the semiconductor device to be measured; therefore, in fact, it is difficult to install such a fail memory in the semiconductor memory device or the semiconductor device, and consequently, it is not possible to carry out the redundant analysis.
[An Arrangement in Which One Bit Data is Read Out Per One Memory Cell]
In order to solve the above-mentioned problems, Japanese Patent Laying-Open No. 2001-6387 discloses the following arrangement.
FIG. 29 is a schematic block diagram that shows the entire structure of a dynamic-type semiconductor memory device (hereinafter, referred to as DRAM) 9000 disclosed by Japanese Patent Laying-Open No. 2001-6387, where one-bit data is read out per sub-memory alley.
Referring to FIG. 29, DRAM 9000 is provided with a control signal input terminal group 11 for receiving a control signal such as a row address strobe signal/RAS, an address input terminal group 13 for receiving address signals A0 to Ai (i: natural number) and a data input/output terminal group 15 for carrying out data input/output operations.
DRAM 9000 is further provided with a control circuit 26 for generating an internal control signal for controlling the entire operation of DRAM 9000 in accordance with a control signal; an internal control signal bus 72 for transmitting the internal control signal; an address buffer 30 for generating an internal address signal upon receipt of an external address signal from address input terminal group 13; and a memory cell array 100 having a plurality of memory cells MC arranged in a matrix manner.
Here, it is assumed that one-bit data is read out per one memory cell array 100.
The internal address signals refer to, for example, mutually complementary internal row address signals RA0-13 and/RA0-13 generated from external row address signal RA0-13 and mutually complementary internal column address signals CA0-8 and /CA0-8 generated from external row address signal CA0-8.
In the same manner as memory cell array section 8010 shown in FIG. 28, a memory cell array 100 shown in FIG. 29 includes a normal memory cell array 100R, a spare row SR and a spare column SC.
In memory cell array 100 also, with respect to spare rows SR, two spare rows SR1 and SR2 are installed, and with respect to spare columns SC, two spare columns SC1 and SC2 are installed.
DRAM 9000 is further provided with a built-in self test circuit (hereinafter, referred to as BIST circuit) 7000 for detecting a defective memory cell in DRAM 9000 and for carrying out a testing operation for replacing it with a spare row SR or a spare column SC.
During a normal operation, BIST circuit 7000, which is controlled by a control circuit 26, outputs an internal row address signal and an internal column address signal from address buffer 30, as they are, to a row decoder, a spare row decoder 42, a column decoder 50 and a spare column decoder 52 respectively. Moreover, during the normal operation, BIST circuit 7000 receives written data, which has been supplied from data input/output terminal group 15, subjected to a buffer process by an input/output buffer 85, and outputted from a writing driver 80, and outputs the data as it is to a row selection gate 200.
In contrast, during a testing operation, BIST circuit 7000 gives not an internal address signal from address buffer 30, but an internal address signal generated inside BIST circuit 7000, to row decoder 40, spare row decoder 42, column decoder 50 and spare column decoder 52 respectively. Moreover, not data supplied from writing driver 80, but testing-use writing data TD, generated inside BIST circuit 7000, is given to a column selection gate 200 so that the test data is written in memory cell array 100.
Upon completion of the writing operation in such a testing operation, BIST circuit 7000 again generates an internal address signal so as to read out written data successively. In accordance with the results of comparisons between the read data and expected value data ED, BIST circuit 7000 successively detects the position of a defective memory cell in a normal memory cell array 100R, and determines what combination between spare row SR and spare column SC is used for replacing a plurality of defective row addresses and defective column addresses corresponding to such a plurality of defective memory cells.
In accordance with the determination as described above, an external tester gives instructions to a repair device so that, for example, the repair device trims fuse elements in spare row decoder 42 and spare column decoder 52.
FIG. 30 is a schematic block diagram that explains the arrangement of an address replacement determining device 8000 contained in BIST circuit 7000.
First, prior to explaining the structure of address replacement determining device 8000, an explanation will be briefly given of a processing sequence for replacing the defective addresses in memory cell array 100 in FIG. 29 with spare row SR and spare column SC.
In the following description, it is assumed that a defective memory cell distribution that is the same as the defective memory cells in memory cell array section 8010 shown in FIG. 28 occurs also in memory cell array 100.
Therefore, as shown in FIG. 28, in the case when eight defective memory cells, that is, defective memory cells DBM1 to DBM8, exist, if an attempt is made to detect these defective memory cells DBM1 to DBM8 while the row address is being changed with the column address being also changed, the existence of the defective memory cells is detected in the order of detective memory cells DBM1 to DBM8.
Here, in the case when the defective addresses corresponding to these defective memory cells are replaced with two spare rows SR1 and SR2 and two spare columns SC1 and SC2, there are two cases in which all the defective memory cells are repaired and in which they are not repaired, depending on in what order the spare row and spare column are replaced by normal memory cell row or normal memory cell column corresponding to the defective memory cells.
For example, a defective memory cell DBM1 (row address RF1, column address CF1) is replaced by spare row memory cell SRM1, defective memory cells DBM2 to DBM4 (row address is RF2 in common with each other, column addresses, CF2, CF3, CF4) are replaced by the second spare row memory cell SRM2, defective memory cells DBM5 to DBM7 (column address is CF5 in common with each other, row addresses are respectively RF3, RF4 and RF5) are replaced by the first spare column memory cell SCM1, and defective memory cell DBM8 (row address RF8, column address CF8) is replaced by the second spare column memory cell SCM2; thus, in this case, it is possible to replace all the defective memory cells DBM1 to DBM8 by using two spare rows SR1 and SR2 and two spare columns SC1 and SC2.
However, for example, in the case when the following processes are successively carried out: defective memory cell DBM1 is first replaced by the first spare column memory cell SCM1, defective memory cell DBM2 is then replaced by the second spare column memory cell SCM2, the third defective memory cell DBM3 that is successively detected is replaced by the first spare row memory cell SRM1, and the defective memory cell DBM5 that fifth appears is replaced by the second spare row memory cell SRM2; it is not possible to repair all the defective memory cells by replacing them with two spare rows and two spare columns.
As described above, in the process where defective memory cells are replaced by spare rows or spare columns while the defective memory cells are successively detected, there are cases where detective memory cells can be repaired and where they can not repaired depending not only on the distribution of defective memory cells in the normal memory array, but also on what order the replacing process with the spare row and the spare column is carried out in.
Here, in the case when there are two spare rows and two spare columns, with respect to in what order the detective memory cells successively detected are replaced with spare rows and spare columns, there are the following six combinations, depending on in what step in the four steps of replacements they are replaced with spare rows or spare columns.
In the following description, the replacement with a spare row is represented by R, and the replacement with a spare column is represented by C.
Case 1: Rxe2x86x92Rxe2x86x92Cxe2x86x92C
Case 2: Rxe2x86x92Cxe2x86x92Rxe2x86x92C
Case 3: Rxe2x86x92Cxe2x86x92Cxe2x86x92R
Case 4: Cxe2x86x92Rxe2x86x92Rxe2x86x92C
Case 5: Cxe2x86x92Rxe2x86x92Cxe2x86x92R
Case 6: Cxe2x86x92Cxe2x86x92Rxe2x86x92R
In the case when all the defective memory cells are finally replaced with two spare rows and two spare columns and repaired, within the above-mentioned 6 orders, the order of the replacing process with spare rows and spare columns, which can carry out the complete repair, is definitely contained.
Address replacement determining device 8000 shown, in FIG. 30, has an arrangement for processing the six systems in parallel with each other so as to discriminate the above-mentioned six cases in parallel with each other.
Referring to FIG. 30, address replacement determining device 8000 is provided with first to sixth replacement determining sections 8100.1 to 8100.6 each of which can determine whether or not the defective addresses may be repaired by replacing them through the replacing process of the defective addresses in accordance with the above-mentioned cases 1 to 6.
Address replacement determining device 8000 is further provided with: row address memory sections RM1 to RM6 for storing row addresses to be replaced with two spare rows in association with the first replacement determining section 8100.1 to the sixth replacement determining section 8100.6, and column address memory sections CM1 to CM6 for storing column addresses to be replaced with the two column addresses.
For example, in the case of the above-mentioned case 1, a row address memory section RM1 and a column address memory section CM1 are respectively provided in association with the first replacement determining section 8100.1 that is prepared for carrying out the replacement with spare columns twice after successively carrying out the replacing processes twice by using spare rows.
Row address storing portion RM1 is provided with a storing cell train MCR11 for storing row addresses to be replaced by the first spare row SR1 and a storing cell train MCR12 for storing row addresses to be replaced by the second spare row SR2.
Here, column address storing portion CM1 is provided with a storing cell train MCC11 for storing column addresses to be replaced with the first spare column SC1 and a storing cell train MCC12 for storing column addresses to be replaced by the second spare column SC2.
The first replacement determining section 8100.1, which corresponds to the case 1 as described above, deals with the storing cell trains within the corresponding row address storing portion RM1 and column address storing portion CM1, and makes a determination as to whether or not the internal address signal is to be written into the storing cell trains in the order of the storing cell train MCR11, storing cell train MCR12, storing cell train MCC11 and storing cell train MCC12 each time the pass/fail signal P/F is activated.
In association with storing cell trains MCR11, MCR12, MCC11 and MCC12, pre-charging circuits CPR11, CPR12, CPC11 and CPC12 are installed. Each of the pre-charging circuits CPR11 to CPC12 pre-charges each of matching determining lines MHLs installed in association with corresponding storing cell trains MCR11 to MCC12 to a xe2x80x9cHxe2x80x9d level in accordance with a signal xcfx86.
Storing cell trains MCR11 and MCR12 are respectively installed in association with 14 pairs of internal row address signals RA0, /RA0 to RA13, /RA13, and are provided with content addressable memory cells (hereinafter, referred to as xe2x80x9cCAM cellxe2x80x9d) for storing the level of these signals.
In the same manner, storing cell trains MCC11 and MCC12 are respectively installed in association with pairs of internal column address signals CA0, /CA0 to CA8, /CA8, and provided with CAM cells for storing the level of these signals.
CAM cells in row address storing portion RM1 and column address storing portion CM1 respectively store the level of the corresponding internal row address signal or internal column address signal in response to the change of the writing activation line TWL to the active level (xe2x80x9cHxe2x80x9d level) in accordance with the instruction of the corresponding first replacement determining section 8100.1.
Here, the level of the matching determining line MHL that is pre-charged to the xe2x80x9cHxe2x80x9d level, is maintained at the xe2x80x9cHxe2x80x9d level, in the case when the level of the address signals that have been stored by the storing cell trains is coincident with the level of the internal address signal RA0, /RA0 to RA13, /RA13 or the internal column address signals CA0, /CA0 to CA8, /CA8 that have been given to the address replacement determining device 8000 at this time. In contrast, if not coincident, the matching determining line MHL is set to the xe2x80x9cLxe2x80x9d level.
Moreover, in association with storing cell trains MCR11, MCR12, MCC11 and MCC12, flip-flop circuits SFR11, SFR12, SFC11 and SFC12 are respectively installed. The levels of the flip-flop circuits SFR11 to SFC12 have been reset by a reset signal RST before a testing operation is started, and are set in response to the active state (xe2x80x9cHxe2x80x9d) of the writing selection line TWL of the corresponding storing cell train.
The second replacement determining section 8100.2, which corresponds to the case 2, is provided with row address storing portion RM2 and column address storing portion CM2 so as to deal with alternate replacing process by the spare row and replacing process by the spare column. The second replacement determining section 8100.2 deals with the storing cell trains within the corresponding row address storing portion RM2 and column address storing portion CM2, and makes a determination as to whether or not the internal address signal is to be written into the storing cell trains in the order the storing cell train MCR21, storing cell train MCC21, storing cell train MCR22 and storing cell train MCC22 each time the pass/fail signal P/F is activated. The other structure is the same as the first replacement determining section 8100.1.
With respect to each of the third to sixth replacement determining sections 8100.3 to 8100.6, only the corresponding memory cell column and the order of the writing to the corresponding memory cell column are different in accordance with the cases 3 to 6, with the other structures being the same as that of the replacement determining section 8100.1; therefore, the description thereof is omitted.
In the above-mentioned arrangement, a brief explanation will be given of the operation of the replacement determining section 8100.1.
In other words, for example, at the time when the pass/fail signal P/F is activated, the first replacement determining section 8100.1 allows the writing selection line TWL of the storing cell train MCR11 to be activated. Accordingly, the level of flip-flop circuit SFR11 corresponding to storing cell train MCR11 is set so that the writing of an address signal to the storing cell train MCR11 is recorded as data.
Successively, at the time when the pass/fail signal P/F is again activated, the respective CAM cells compare the internal row address signal held in the storing cell train MCR11 with the level of the internal row address signal at this time, and in accordance with the result of the comparison, the level of the matching detection line MHL of the storing cell train MCR11 is driven. Accordingly, the first replacement determining section 8100.1 does not allow the storing cell train MCR12 to activate in the case when the internal row address that has been held in the storing cell train MCR11 is coincident with the internal row address corresponding to a newly detected defective memory cell.
In contrast, in the case when the internal row address that has been stored in the storing cell train MCR11 is not coincident with the internal row address corresponding to a newly detected defective memory cell, the first replacement determining section 8100.1 makes active the writing selection line TWL of the storing cell train MCR12 that is to be second activated.
Then, the internal row address corresponding to the newly detected defective memory cell is written in the second storing cell train MCR12, and the level of the flip-flop circuit SFR12 corresponding to the storing cell train MCR12 is set.
Thereafter, in the same manner, each time a defective memory cell is detected, and in the case when the internal row address or the internal column address that has been held in the storing cell train is not coincident with the internal row address or the internal column address corresponding to the newly detected defective memory cell, the storing cell trains are successively activated in the order of case 1 corresponding to the first replacement determining section 8100.1.
Here, in the case when the internal row address or the internal column address that has been stored in the storing cell train is coincident with the internal row address or the internal column address corresponding to the newly detected defective memory cell, the first replacement determining section 8100.1 does not allow the storing cell train corresponding to the next order to be activated.
Finally, in the case when, after the normal memory cells have been tested in the built-in test, the internal row addresses and the internal column addresses of all the detective memory cells that have been successively detected are coincident with the internal row address and the internal column address that have been stored in the row address storing portion MR1 and the column address storing portion CM1, it is determined that it is possible to replace and repair all the defective memory cells by replacing the defective memory cells with the spare row or the spare column in the order corresponding to the first replacement determining section 8100.1. The result of the determination is outputted from address replacement determining device 8000 as a repair fail signal RF.
As described above, the same structures as the first replacement determining section 8100.1 and the corresponding row address storing portion RM1 and the column address storing portion CM1 are also installed on the second replacement determining section 8100.2 to the sixth replacement determining section 8100.6. Moreover, the second replacement determining section 8100.2 to the sixth replacement determining section 8100.6 respectively correspond to case 2 to case 6 so that the respective replacement determining sections successively activate the storing cell trains of the row address storing portion and the storing cell trains of the column address storing portion in accordance with the corresponding order.
Therefore, as illustrated in FIG. 29, if it is possible to repair the defective memory cells in the normal memory cell array 100R by using two spare rows and two spare columns, the repair fail signal RF from at least any one of the first replacement determining section 8100.1 to the sixth replacement determining section 8100.6 maintains a non-active state (xe2x80x9cLxe2x80x9d level) even at the time when the last defective memory cell has been detected.
In accordance with this, the repair fail signal RF reads out the internal row address signal and the internal column address signal held in the row address storing portion and column address storing portion corresponding to the replacement determining section in a non-active state. In response to the internal row address signal and the internal column address signal thus read, it is possible to program the row addresses and the column addresses to be replaced in spare row decoder 42 and spare column decoder 52.
In the arrangement of BIST circuit 7000 as described above, even when the memory capacity of the semiconductor memory device to be measured is large, the testing circuit scale can be reduced; therefore, it is easily built inside the semiconductor memory device.
(Problems with the Structure from Which Data Having a Plurality of Bits is Read Per Memory Cell Array)
FIG. 31 is a conceptual drawing that explains a replacing operation by using a redundant memory cell array where the memory cell array 100 is divided into two sub-memory arrays 100.0 and 100.1.
In the embodiment shown in FIG. 31, when one word line WL is activated, data reading operations are simultaneously carried out from the bit lines BL0, /BL0 of the sub-memory cell array 100.0 and bit lines BL1, /BL1 of the sub-memory cell array 100.1.
In the above-mentioned structure, when the above-mentioned replacement of the redundant memory cell array is carried out, the following problems will arise.
In other words, in the case when the replacement to the redundant memory cell is carried out in the order from the redundant memory cell column to the redundant memory cell row, if both of the memory cells DBM1 and DBM2 belonging to the same memory cell row are defective memory cells, for example, it is possible to replace one of the defective memory cells DBM1 by the redundant memory cell column SC.
However, in the structure of the semiconductor memory device 9000 explained in FIG. 29, it is not possible to simultaneously replace the two memory cell columns. Therefore, in the case when, after the process in which the memory cell column containing the detective memory cell DBM1 is replaced by the redundant memory cell column SC, a defective memory cell DBM3 belonging to a memory cell row different from the defective memory cell DBM1 is detected, the memory cell row containing this defective memory cell DBM3 is successively replaced by the redundant memory cell row SR.
However, such a replacing process fails to repair the defective memory cell DBM2. In addition to the failure to repair, since the defective memory cell DBM1 specified by the same row address and the same column address has been repaired with respect to the BIST circuit 2000, an erroneous determination that both the memory cell DBM1 and DBM2 have been repaired might be made although the defective memory cell DBM2 has not been repaired.
In other words, in the case when the memory cell array 100 is divided into two sub-memory cell arrays 100.0 and 100.1 and when in accordance with the activation of one word line WL, data is simultaneously read from a plurality of memory cells (for example, two memory cells), the structure of BIST circuit 2000 simply explained by FIGS. 29 and 30 might fail to correctly determine whether or not the repair by the redundant memory cell array has been successfully made, in some cases.
The objective of the present invention is to provide a semiconductor integrated circuit device with a built-in test circuit which, in the case when a plurality of memory cells are simultaneously selected in response to an activation of the same word line, detects a defective memory cell, and also carries out an analysis for replacing the defective memory cell with a redundant memory cell.
In short, the present invention is a semiconductor integrated circuit device that is provided with a memory cell array, a normal memory cell selection circuit, a preliminarily memory cell selection circuit and a self testing circuit.
A plurality of memory cells, each storing memory data, are placed in a matrix format on the memory cell array. The memory cell array is divided into at least a first and a second sub-memory cell arrays. With respect to the memory cell array, each of the first and second sub-memory cell arrays is provided with a normal memory cell array containing a plurality of normal memory cells and a preliminarily memory cell array containing a plurality of preliminarily memory cells.
A normal memory cell selection circuit selects at least one of the memory cell row and the memory cell column that is in common with the normal memory cell array in the first and second sub-memory cell array. In the case when a defective memory cell exists in the normal memory cell array, a preliminarily memory cell selection circuit selects either one of the memory cell row and memory cell column in the preliminarily memory cell array commonly from the preliminarily memory cell array of the first and the second sub-memory cell array, in place of either one of the common memory cell row and memory cell column to be selected by the normal memory cell selection circuit.
A self-testing circuit detects a defective memory cell in the normal memory cell, and carries out a test for determining which preliminarily memory cell is used for replacing the defective memory cell. The self-testing circuit is installed in each of the first and second sub-memory cell arrays, and includes a plurality of primary replacement determining circuits which make a determination as to which preliminarily memory cell is used for the replacement, supposing that the selection of a memory cell from the first and second sub-memory cell arrays and the replacement to the preliminarily memory cell are carried out independently from each other, and outputs the results of determination.
More preferably, the self-testing circuit further includes a secondary replacement determining circuit. Based upon the results of determination from the plurality of primary replacement determining circuits, the secondary replacement determining circuit determines a defective row address and a defective column address that form the replacement subjects in the case when the memory cell array is replaced and repaired, under the regulated condition that either one of the memory cell row and the memory cell column in the preliminarily memory cell array is commonly selected by the primarily memory cell array of the first and second sub-memory cell arrays in place of either one of the common memory cell row and memory cell column to be selected by the normal memory cell selection circuit.
Therefore, the advantage of the present invention is that it is possible to detect a defective memory cell and to carry out a redundant analysis by using a comparatively small circuit scale, in the case when one memory cell is simultaneously selected for each of sub-memory cell arrays, and also to install a testing circuit having a redundant analyzing function in a semiconductor integrated circuit device itself.
Another advantage of the present invention is that since the secondary analysis can be executed within the semiconductor integrated circuit device, it becomes possible to further reduce the load of the tester device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.